HOPE


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Introduction

 

Projet HOPE - ANR 12 INSE 0003

Projet ANR HOPE

Hierarchically Organized Power/Energy management


The ANR Project HOPE aims to provide an appropriate framework to assist designers in the early steps of systems on chip design (SoC) where energy/power/temperature/performance are primary constraints.

The design of a hardware/software efficient architecture based on an interconnection of IPs and including embedded software (the functional part) while satisfying performance/cost constraints, is already recognized as a real difficult problem. Reducing power consumption in a functional architecture consists in extending the architecture with power-oriented components (e.g. power switches, retention registers,…) able to rely the power controls provided by a power management strategy. However, embedding the power architecture in the functional architecture can result in some violation of performance constraints or even to an alteration of the feature itself. Dealing with this problem involves considering the system as a whole which leads to consider appropriate levels of abstraction for modeling the complete system. SystemC-TLM is a good candidate for modeling behavior at transaction level but currently very little research and development work are made at this level to explore/validate a power-oriented architecture along with a functional architecture.

The Project HOPE aims to propose an approach for TLM modeling of components and their associated controls involved in a power architecture in strong relationship with the functional architecture. In addition, the project will address exploration techniques of power architecture so as to identify at system level solutions that match performance/temperature /energy/cost constraints. In the project HOPE we will address as well a hierarchical approach for system power management to limit the complexity of a centralized power manager and to be able to deal with technologies such as SiP (System in Package) and 3D silicon. The aim is also to rely on well-established standards ( UPF , IP -XACT , SystemC OSCI TLM- 2.0) to adhere to standard design flows.


News : STAGES de Master/Ingénieur 2017

Deux stages Master/Ingénieur sont proposés sur ce thème pour 2017 au LEAT :

Etude d’un module générique de gestion de puissance dans un OS pour systèmes embarqués.

Edition graphique en vue de simulation d’une spécification d’un Power Intent d’une architecture de système sur puce.


Doctoral thesis : 

  • Ameni Khecharem (INRIA), "Une approche de méta-modélisation pour la représentation multi-vues des architectures hétérogènes embarquées", (3/05/2016)
  • Hend Affes (LEAT) TLM modelling of architecture and control of power management structure for system on chips. (18/12/2015)
  • Mr. C. E. Gómez Cárdenas (INRIA)  : " Modeling Functional and Non-Functional Properties of Systems Based on A Multi-View Approach", 20/12/2013
  • Ms. Ons Sboui-Mbarek (LEAT) : A SystemC-TLM-oriented approach for modeling/design low power architecture based on an abstraction of UPF (Unified Power Format), 29/05/2013

Master Report 2015 : Analysis of the IoT oriented ecosystem in French Region PACA. This study was conducted by the GREDEG laboratory and supported by the ANR HOPE project with the assistance and the guidance of the SCS Cluster.



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